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| DISCRETE SEMICONDUCTORS DATA SHEET BF1201; BF1201R; BF1201WR N-channel dual-gate PoLo MOS-FETs Product specification Supersedes data of 1999 Dec 01 2000 Mar 29 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs FEATURES * Short channel transistor with high forward transfer admittance to input capacitance ratio * Low noise gain controlled amplifier * Partly internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. APPLICATIONS * VHF and UHF applications with 3 to 9 V supply voltage, such as digital and analogue television tuners and professional communications equipment. handbook, 2 columns 4 BF1201; BF1201R; BF1201WR PINNING PIN 1 2 3 4 DESCRIPTION source drain gate 2 gate 1 Top view MSB035 handbook, 2 columns 3 4 2 1 BF1201R marking code: LBp Fig.2 Simplified outline (SOT143R). 3 page 3 4 DESCRIPTION Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1201, BF1201R and BF1201WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively. QUICK REFERENCE DATA SYMBOL VDS ID Ptot yfs Cig1-ss Crss F Xmod Tj PARAMETER drain-source voltage drain current total power dissipation forward transfer admittance input capacitance at gate 1 reverse transfer capacitance noise figure cross-modulation operating junction temperature CAUTION This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B. 2000 Mar 29 2 f = 1 MHz f = 400 MHz input level for k = 1% at 40 dB AGC CONDITIONS - - - 23 - - - 105 - MIN. - - - 28 2.6 15 1 - - TYP. MAX. 10 30 200 35 3.1 30 1.8 - 150 UNIT V mA mW mS pF fF dB dBV C 1 Top view 2 MSB014 2 Top view 1 MSB842 BF1201 marking code: LAp. BF1201WR marking code: LA Fig.1 Simplified outline (SOT143B). Fig.3 Simplified outline (SOT343R). Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDS ID IG1 IG2 Ptot PARAMETER drain-source voltage drain current (DC) gate 1 current gate 2 current total power dissipation BF1201; BF1201R BF1201WR Tstg Tj Note 1. Ts is the temperature of the soldering point of the source lead. THERMAL CHARACTERISTICS SYMBOL Rth j-s BF1201; BF1201R BF1201WR PARAMETER thermal resistance from junction to soldering point storage temperature operating junction temperature Ts 113 C; note 1 Ts 109 C; note 1 - - CONDITIONS - - - - BF1201; BF1201R; BF1201WR MIN. MAX. 10 30 10 10 200 200 +150 150 V UNIT mA mA mA mW mW C C -65 - VALUE 185 155 UNIT K/W K/W handbook, halfpage 250 Ptot (mW) MCD934 200 (2) (1) 150 100 50 0 0 50 100 150 Ts (C) 200 (1) BF1201WR. (2) BF1201 and BF1201R. Fig.4 Power derating curve. 2000 Mar 29 3 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs STATIC CHARACTERISTICS Tj = 25 C; unless otherwise specified. SYMBOL V(BR)DSS PARAMETER drain-source breakdown voltage CONDITIONS VG1-S = VG2-S = 0; ID = 10 A VG2-S = VDS = 0; IG1-S = 10 mA VG1-S = VDS = 0; IG2-S = 10 mA VG2-S = VDS = 0; IS-G1 = 10 mA VG1-S = VDS = 0; IS-G2 = 10 mA VG2-S = 4 V; VDS = 5 V; ID = 100 A VG1-S = VDS = 5 V; ID = 100 A BF1201; BF1201R; BF1201WR MIN. 10 6 6 0.5 0.5 0.3 0.3 11 - - MAX. - - - 1.5 1.5 1.0 1.2 19 50 20 UNIT V V V V V V V mA nA nA V(BR)G1-SS gate 1-source breakdown voltage V(BR)G2-SS gate 2-source breakdown voltage V(F)S-G1 V(F)S-G2 VG1-S(th) VG2-S(th) IDSX IG1-SS IG2-SS Note 1. RG1 connects G1 to VGG = 5 V. forward source-gate 1 voltage forward source-gate 2 voltage gate 1-source threshold voltage gate 2-source threshold voltage drain-source current gate 1 cut-off current gate 2 cut-off current VG2-S = 4 V; VDS = 5 V; RG1 = 62 k; note 1 VG2-S = VDS = 0; VG1-S = 5 V VG1-S = VDS = 0; VG2-S = 4 V DYNAMIC CHARACTERISTICS Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; ID = 15 mA; unless otherwise specified. SYMBOL yfs Cig1-ss Cig2-ss Coss Crss F PARAMETER forward transfer admittance input capacitance at gate 1 input capacitance at gate 2 output capacitance noise figure f = 1 MHz f = 1 MHz f = 1 MHz f = 10.7 MHz; GS = 20 mS; BS = 0 f = 400 MHz; YS = YS opt f = 800 MHz; YS = YS opt Gtr power gain f = 200 MHz; GS = 2 mS; BS = BS opt; GL = 0.5 mS; BL = BL opt; f = 400 MHz; GS = 2 mS; BS = BS opt; GL = 1 mS; BL = BL opt; f = 800 MHz; GS = 3.3 mS; BS = BS opt; GL = 1 mS; BL = BL opt; Xmod cross-modulation input level for k = 1%; fw = 50 MHz; funw = 60 MHz; note 1 at 0 dB AGC at 10 dB AGC at 40 dB AGC Note 1. Measured in Fig.21 test circuit. 90 - 105 - 95 - - - - dBV dBV dBV CONDITIONS pulsed; Tj = 25 C MIN. 23 - - - - - - - - - - TYP. 28 2.6 1.1 0.9 15 5 1 1.9 33.5 29 24 MAX. 35 3.1 - - 30 7 1.8 2.5 - - - UNIT mS pF pF pF fF dB dB dB dB dB dB reverse transfer capacitance f = 1 MHz 2000 Mar 29 4 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR handbook, halfpage 25 MCD935 ID (mA) VG2-S = 4 V 3.5 V 3V handbook, halfpage 24 MCD936 20 2.5 V ID (mA) 16 VG1-S = 1.8 V 1.7 V 1.6 V 1.5 V 1.4 V 15 2V 10 8 1.5 V 5 1V 0 0 0.5 1 1.5 2 2.5 VG1-S (V) 0 0 2 4 6 8 1.3 V 1.2 V 10 VDS (V) VDS = 5 V. Tj = 25 C. VG2-S = 4 V. Tj = 25 C. Fig.5 Transfer characteristics; typical values. Fig.6 Output characteristics; typical values. handbook, halfpage 100 MCD937 IG1 (A) VG2-S = 4 V handbook, halfpage 40 MCD938 3.5 V 80 3V 60 2.5 V 40 2V 20 1.5 V 0 0 0.5 1 1.5 2 2.5 VG1-S (V) yfs (mS) 30 VG2-S = 4 V 3.5 V 20 3V 10 2V 2.5 V 0 0 5 10 15 20 25 ID (mA) VDS = 5 V. Tj = 25 C. VDS = 5 V. Tj = 25 C. Fig.7 Gate 1 current as a function of gate 1 voltage; typical values. Fig.8 Forward transfer admittance as a function of drain current; typical values. 2000 Mar 29 5 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR handbook, halfpage 16 MCD939 handbook, halfpage 20 MCD940 ID (mA) 12 ID (mA) 16 12 8 8 4 4 0 0 10 20 30 40 50 IG1 (A) 0 0 1 2 3 4 VGG (V) 5 VDS = 5 V; VG2-S = 4 V. Tj = 25 C. VDS = 5 V; VG2-S = 4 V; Tj = 25 C. RG1 = 62 k (connected to VGG); see Fig.21. Fig.9 Drain current as a function of gate 1 current; typical values. Fig.10 Drain current as a function of gate 1 supply voltage (= VGG); typical values. handbook, halfpage 25 MCD941 ID (mA) RG1 = 39 k 47 k 56 k 62 k 68 k 82 k handbook, halfpage 20 MCD942 ID (mA) 20 16 100 k 12 VGG = 5 V 4.5 V 4V 3.5 V 15 10 8 3V 5 4 0 0 2 4 6 8 10 VGG = VDS (V) 0 0 2 4 VG2-S (V) 6 VG2-S = 4 V; Tj = 25 C. RG1 connected to VGG; see Fig.21. VDS = 5 V; Tj = 25 C. RG1 = 62 k (connected to VGG); see Fig.21. Fig.11 Drain current as a function of gate 1 (= VGG) and drain supply voltage; typical values. Fig.12 Drain current as a function of gate 2 voltage; typical values. 2000 Mar 29 6 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR handbook, halfpage 60 MCD943 VGG = 5 V handbook, halfpage gain 0 MCD944 IG1 (A) 40 4.5 V 4V 3.5 V 3V reduction (dB) -10 -20 -30 20 -40 0 0 2 4 VG2-S (V) 6 -50 0 1 2 3 VAGC (V) 4 VDS = 5 V; Tj = 25 C. RG1 = 62 k (connected to VGG); see Fig.21. VDS = 5 V; VGG = 5 V; RG1 = 62 k; f = 50 MHz; Tamb = 25 C. Fig.13 Gate 1 current as a function of gate 2 voltage; typical values. Fig.14 Typical gain reduction as a function of the AGC voltage; see Fig.21. handbook, halfpage 120 MCD945 Vunw (dBV) 110 handbook, halfpage 20 MCD946 ID (mA) 16 12 100 8 90 4 80 0 10 20 30 40 50 gain reduction (dB) 0 0 10 20 30 40 50 gain reduction (dB) VDS = 5 V; VGG = 5 V; RG1 = 62 k; f = 50 MHz; funw = 60 MHz; Tamb = 25 C. VDS = 5 V; VGG = 5 V; RG1 = 62 k; f = 50 MHz; Tamb = 25 C. Fig.15 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.21. Fig.16 Drain current as a function of gain reduction; typical values; see Fig.21. 2000 Mar 29 7 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR 102 handbook, halfpage Yis (mS) 10 MCD947 103 handbook, halfpage yrs (S) 102 bis gis yrs 10 rs MCD948 -103 rs (deg) -102 1 -10 10-1 10 102 f (MHz) 103 1 10 102 f (MHz) -1 103 VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. Fig.17 Input admittance as a function of frequency; typical values. Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. 102 handbook, halfpage yfs (mS) MCD949 -102 fs (deg) handbook, halfpage 10 MCD950 yfs Yos (mS) 1 bos 10 fs -10 10-1 gos 1 10 102 f (MHz) -1 103 10-2 10 102 f (MHz) 103 VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. VDS = 5 V; VG2 = 4 V. ID = 15 mA; Tamb = 25 C. Fig.19 Forward transfer admittance and phase as a function of frequency; typical values. Fig.20 Output admittance as a function of frequency; typical values. 2000 Mar 29 8 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR handbook, full pagewidth VAGC R1 10 k C1 4.7 nF C3 4.7 nF C2 RGEN 50 VI R2 50 4.7 nF RG1 DUT 2.2 H C4 4.7 nF L1 RL 50 VGG VDS MGS315 Fig.21 Cross-modulation test set-up. Table 1 f (MHz) 50 100 200 300 400 500 600 700 800 900 1000 Table 2 Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C s11 MAGNITUDE (ratio) 0.987 0.985 0.978 0.976 0.949 0.928 0.905 0.882 0.860 0.838 0.818 ANGLE (deg) -4.72 -9.39 -18.59 -27.74 -36.59 -45.08 -53.26 -61.07 -68.48 -75.55 -82.23 s21 MAGNITUDE (ratio) 2.775 2.774 2.731 2.671 2.599 2.501 2.400 2.297 2.199 2.096 1.997 ANGLE (deg) 174.6 169.5 159.1 148.8 138.8 129.1 119.8 110.9 102.4 94.2 86.3 s12 MAGNITUDE (ratio) 0.0006 0.0010 0.0019 0.0026 0.0032 0.0035 0.0035 0.0033 0.0029 0.0024 0.0021 ANGLE (deg) 88.8 86.7 79.7 74.2 69.9 65.9 64.6 65.7 69.1 83.3 103.8 s22 MAGNITUDE (ratio) 0.997 0.997 0.996 0.994 0.992 0.989 0.986 0.982 0.979 0.975 0.971 ANGLE (deg) -1.84 -3.37 -6.72 -10.02 -13.33 -16.55 -19.64 -22.63 -25.54 -28.44 -31.42 Noise data: VDS = 5 V; VG2-S = 4 V; ID = 15 mA; Tamb = 25 C f (MHz) 400 800 Fmin (dB) 1 1.9 opt (ratio) 0.825 0.753 (deg) 38.93 70.65 Rn () 50 38.75 2000 Mar 29 9 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs PACKAGE OUTLINES Plastic surface mounted package; 4 leads BF1201; BF1201R; BF1201WR SOT143B D B E A X y vMA HE e bp wM B 4 3 Q A A1 c 1 b1 e1 2 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.45 0.15 Q 0.55 0.45 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT143B REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-02-28 2000 Mar 29 10 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR Plastic surface mounted package; reverse pinning; 4 leads SOT143R D B E A X y vMA HE e bp wM B 3 4 Q A A1 c 2 b1 e1 1 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 max 0.1 bp 0.48 0.38 b1 0.88 0.78 c 0.15 0.09 D 3.0 2.8 E 1.4 1.2 e 1.9 e1 1.7 HE 2.5 2.1 Lp 0.55 0.25 Q 0.45 0.25 v 0.2 w 0.1 y 0.1 OUTLINE VERSION SOT143R REFERENCES IEC JEDEC EIAJ SC-61B EUROPEAN PROJECTION ISSUE DATE 97-03-10 99-09-13 2000 Mar 29 11 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1201; BF1201R; BF1201WR Plastic surface mounted package; reverse pinning; 4 leads SOT343R D B E A X y HE e vMA 3 4 Q A A1 c 2 wM B bp e1 b1 1 Lp detail X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.8 A1 max 0.1 bp 0.4 0.3 b1 0.7 0.5 c 0.25 0.10 D 2.2 1.8 E 1.35 1.15 e 1.3 e1 1.15 HE 2.2 2.0 Lp 0.45 0.15 Q 0.23 0.13 v 0.2 w 0.2 y 0.1 OUTLINE VERSION SOT343R REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-21 2000 Mar 29 12 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development BF1201; BF1201R; BF1201WR DEFINITIONS (1) This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Preliminary specification Qualification Product specification Production Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2000 Mar 29 13 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs NOTES BF1201; BF1201R; BF1201WR 2000 Mar 29 14 Philips Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs NOTES BF1201; BF1201R; BF1201WR 2000 Mar 29 15 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 603504/02/pp16 Date of release: 2000 Mar 29 Document order number: 9397 750 06901 |
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